The present invention relates to fabrication of patterned metallization in integrated circuits.
The increasing complexity of ULSI circuits has resulted in an increased number of interconnect levels, as well as an increased amount of metal routing in the first metal layer. The patterning of metal is becoming more and more difficult due to the decreasing pitch and the higher topography due to the added layers of interconnect.
One current approach is to planarize the interlevel dielectric before the metal layer is deposited. This can be accomplished by techniques such as chemical-mechanical polishing or nonselective etchback of photoresist or spin-on glass. After the etchback the metal layer is deposited over a more planar surface, which results in a better process window for the metal pattern definition. (The depth of field of high-resolution photolithographic imaging systems is so small that the magnitude of topographic excursions produced by a patterned layer or two can significantly degrade imaging precision.)
The disclosed innovations provide a new twist on such approaches: planarization is now performed in the middle of the metal deposition process.
Modern metallization systems commonly use an adhesion layer and/or a barrier metal in the contact holes. For example, titanium (Ti) is commonly deposited first, as an adhesion layer, followed by titanium nitride (TIN) to provide a diffusion barrier. (Titanium has very good adhesion to silicon oxides.) A rapid thermal anneal (RTA) converts part of the titanium, where it is in contact with silicon, into titanium silicide (which helps to reduce contact resistance, and to prevent diffusion of titanium into the silicon). The majority of the thickness of the conductor (e.g. Al:Si or Al:Cu) is then deposited, followed by a stack etch in which the barrier and adhesion layers are etched along with the main metal layer.
The proposed method performs planarization AFTER the barrier metal has already been deposited. This process planarizes the interlevel dielectric, and removes the barrier metal from the higher areas of topography (where it is not as necessary). This planarization can be done either by chemical-mechanical polishing or by SOG or resist etchback. The resist etchback method is probably safer, since the photoresist will protect the barrier in the contact holes and is easily removed after the etch is done. After the planarization process is complete, the metal is then deposited in the normal fashion, and processing proceeds normally.
According to a disclosed class of innovative embodiments, there is provided: A method for fabricating integrated circuits, comprising the steps of: providing a partially fabricated structure which includes transistors; depositing an interlevel dielectric layer over said transistors; etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; conformally depositing a sacrificial material overall, and nonselectively etching away all of said sacrificial except in said contact holes; said etch being continued for long enough to completely remove said first conductive layer from at least some portions of said interlevel dielectric; and depositing an additional layer of metal overall, and patterning said metal to form desired electrical interconnections among said transistors.
According to another disclosed class of innovative embodiments, there is provided: A method for fabricating integrated circuits, comprising the steps of: providing a partially fabricated structure which includes transistors; depositing an interlevel dielectric layer over said transistors; etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; depositing first and second conductive layers over said interlevel dielectric layer, and on the bottoms of said contact holes; performing planarization to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric; and depositing an additional layer of metal overall, and patterning said metal to form desired electrical interconnections among said transistors.
According to another disclosed class of innovative embodiments, there is provided: A method for fabricating integrated circuits, comprising the steps of: providing a partially fabricated structure which includes transistors; depositing an interlevel dielectric layer over said transistors; etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; performing planarization to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric; and depositing an additional layer of metal overall, and patterning said metal to form desired electrical interconnections among said transistors.
According to another disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: a substrate including at least one monolithic body of semiconductor material, and transistors formed therein; an interlevel dielectric layer overlying said transistors; contact holes extending through said interlevel dielectric layer; a diffusion barrier layer on the bottoms and sidewalls of said contact holes; and a patterned thin-film layer of metal running over said silicon oxynitride layer and extending down into said contact holes, to connect said transistors in a desired electrical configuration; wherein, in at least some locations, said additional metal layer overlies said barrier layer on the top surface of said interlevel dielectric, and in other locations said additional metal layer lies directly on said interlevel dielectric, without said garrier layer therebetween.